DREU Summer 2010                                        Andres Fernandez

Home  Week 1  Week 2  Week 3   Week 4  Week 5  Week 6  Week 7  Week 8   Final Report     Week 8 Report July 19 - 23, 2010 During this week I completed the project's documentation and started working on the Parallel Prefix project. The parallel prefix which consists in doing summation very fast will be implemented onto a Field-Programmable Gate Array ( FPGA) board. The two main components are an adder and an accumulator. These two components will be implemented onto the X block (X language). This will be a single block on the X language which will allow the user to customize the size of this parallel prefix without the need to worry about the insides of the block. You can reach me at fernandez.andres@sbcglobal.net