Week 4 Report
June 21 - 25, 2010
During Week 4, I wired all of the
hardware components for the "
Financial Monte Carlo Simulation
on Architecturally Diverse Systems " project. The
three components that I am attaching together on the FPGA chip
are: the RAM, the multiplier, and the accumulator. The RAM has
32 bit capacity and will be used to store integer data. This
data will be fed into the multiplier which can only accept 2
numbers per clock cycle. After a multiplication
operation, the data becomes 64 bit and feeds into the
accumulator which will take the addition of the current number
with the new data coming in. For next week I would be adding
more modifications to this design so it can be used for
multiple applications.
You can
reach me at fernandez.andres@sbcglobal.net
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DREU Summer 2010