DREU Summer 2010                                        Andres Fernandez

Home  Week 1  Week 2  Week 3   Week 4  Week 5  Week 6  Week 7  Week 8   Final Report     Week 3 Report June 14 - 18, 2010  During Week 3, I started to formulate a way to assign multiple matrixes to a vector onto a FPGA board using the Verilog language. The main problem was that the FPGA chip cannot hold a very large matrix. For example, the matrix I am working on is 1024x1024, so my advisor and I came up with a solution that we should treat it as a vector by vector multiplication. And then stream the data into the chip. The chip will have several MAC (multiplier accumulators) to multiply the data very fast. Also, my advisor suggested CoreGen which is part of the Xilinx ISE WebPack (A Verilog synthesizer), which will automatically code the multiplication and the addition hardware block. All I need to do now is to adjust the scheduling or any other adjustments to reach optimal performance. You can reach me at fernandez.andres@sbcglobal.net