Week 2 Report
June
7 - 11, 2010
During Week
2, there was a hold on my assignment because the source code
which I needed to debug was missing. After consulting with my
advisor, I was temporary reassigned to another project called
"Financial Monte Carlo Simulation on
Architecturally Diverse Systems." This project is to run a simulation on
different architectures. There were three architectures that
were used for this project: the CPU of the computer, the GPU
and the FPGA. My assignment was to code the FPGA using a
Hardware Description Language, the language that I am familiar
with is VERILOG . My supervisor said that I should focus
on getting the Stage 3 of this project onto the FPGA. Stage 3
of the project consisted of using a given equation to
code a matrix multiplication with a vector. Before I started
coding, there was a paper I needed read because it described
the layout to be used in programming the FPGA to run the
matrix multiplication.
You can
reach me at fernandez.andres@sbcglobal.net
|
DREU Summer 2010