Day 5 (8/9):

• It was raining a lot all day.
• Marco gave me a lesson on gate sizing today, which was presumably why he didn't want me to add to the library. We talked about how NMOS and PMOS gates need different widths to equalize the current drawn, which I did totally wrong so I'm glad I had the lesson. Now I understand much better, and will hopefully be able to make the gates correctly.
• The lab group went to lunch today at Andreas' and I had a Greek burger. It was still raining.
• Dr. Bahar, Marco and I were supposed to meet today to give a progress update but since the Smartspice licenses were still being updated, there wasn't really anything to discuss or show and I'm not done with results. So we decided to meet Monday instead, hopefully the licenses will be updated by then.

Day 4 (8/8):

• Today was, again, super unproductive. Ningquan came to me this morning and asked me if he had messed up his Smartspice setup, and when we looked at it we realized the license servers were down. This meant that Smartspice and Smartview weren't working, so not only could I not run any Spice simulations, I couldn't look at the simulations I'd run the other day also.
• Marco emailed me and told me not to make any additions to the library before he came back, so I didn't touch the new circuits I needed to add either.
• I had a really instructive and interesting discussion with Dr. Bahar today about graduate school and what I should be looking for in my adventures through google and so on. I feel like applying to graduate school is even more stressful than applying to undergrad, because it's simultaneously much more specific and much more permanent. I'm very glad I took the time to talk to Dr. Bahar because it really helped.

Day 3 (8/7):

• Not much got done today, unfortunately. This morning I spoke to Dr. Bahar about the problem with the Schmitt trigger gates for higher-fan-in gates and what our options were. She explained to me why we couldn't really afford to go higher than 2 inputs on the schmitt trigger gates because the additional sets of transistors would result in it becoming too high of a stack to meet our area constraints. We decided the best option would be to just make standard versions of the 3 and 4 input gates, and just discard implications that have those larger gates in them. Another option would be to convert it to 2-input like we'd been doing, and it might be interesting to try both options and see how that goes.
• We also had a photoshoot today! That was exciting and awkward. A photographer from the Engineering school came and took pictures of us doing tech-y things (pointing at slides, looking at a computer, etc).
• Then I sat down to look at simulations and choose the best chains to doubly reinforce. When I ssh'd in, it was moving very slowly and then I saw it wouldn't let me copy a new file. Why? I had apparently exceeded my disk quota. I checked and realized the data folder that we use for simulations had exceeded our quota by about 50GB, and deleted as many of the old simulations as I could to ameliorate. At one point I tried to move everything into my home directory, but that only has 10 GB of space, so that didn't work either. I spent some time reading the CCV manuals and things but the fact of the matter was that there are a lot of old simulations that I don't feel comfortable deleting, and what probably happened was the larger simulations were made before and we exceeded our grace period so now the system was just refusing to let me do anything until I deleted 30 GB of material I didn't feel comfortable deleting. So I contacted Marco and hopefully this will get resolved. But now I can't even look at the sims so that's not exciting.

Day 2 (8/6):

• I carefully chose sets of chains for rd73 and misex1 that properly demonstrated many different types of chains (length, activation, etc) and hopefully they will demonstrate different and interesting things.
• Marco sent me the t481 files and chose chains for 5xp1 also, but it turns out because both of them have >2-input gates, the spice generation code chokes on it. The options now are to either convert everything to 2-input, which I think Dr. Bahar and Marco are only doing as like a convenience thing, or to make some Schmitt gates for 3 and 4 input gates, which is more optimal. So I wrote up a NAND3 and a NOR3 just standard, and if Marco gives me the OK hopefully we'll figure something out. I'm not sure if we'll make Schmitt-trigger versions of the larger gates though, because they might be too area-costly.
• I think tomorrow AM I will examine the rd53 and 73 and misex1 results, do the double output reinforcement on the best chains for each, and talk to Dr. Bahar about what to do with outputs that end up not having anything in them (like in misex1, some of the outputs had no chains.)

Day 1 (8/5):

• I have a long list of simulations to do this week, and then I have to analyze them and figure out what qualities are best in our simulation sets and try to integrate them together.
• Today I hoped to do like three different circuits of chain implication sets, but I got really bogged down in figuring out my workflow (as always) and then I ran a ton of rd53 simulations that didn't work at all because I had mistakenly not generated enough noise files. It took me a very long time to figure that out, and so while I also did the prep work for my other circuits, but didn't run any simulations because it may or may not have taken me four hours to understand why the simulations were not working as expected, and another two hours to actually run the simulations correctly.
• Finished simulations today: rd53_chains, all sets