Today, I transferred most of the files from my old computer to the sun box. There are still some straggling files here and there but most of them are moved over. The files are pretty scattered and a lot of them need to be organized more thoroughly. I'll do a readme file later on when I have all the files in, including the ones from the new computer. I also worked some on the wrappers but unfortunately I keep getting fatal errors when I map. This problem is frustrating, as the online documentation is not helpful. The error hopefully will be better tomorrow.

I finished up the pre-lim wrapper tests. I talked to Love about the fatal error that I kept getting and he thought that maybe it was due to some of the temporary files that Xilinx creates and that they somehow might interfere. When I cleaned up the project folder, the syntheses ran no problems. I'm currently working on now doing some more testing with the wrappers and looking at test reversals - can Test 1 map back onto Test 2 and does it matter what order we perform the tasks in?

I finished the data collections that I was running from the past few days. It turns out that Test 1 can map back onto Test 2 pretty smoothly but the results are weird - the number of frames decrease (good) but the number of bits increase (bad). My guess is that there's more overhead involved when going to from Test 2 to Test 1. Also, when I constrained the design to only a subsection of the board, it refused to run well - not only did it give a horrible timing, it took over 7 hours (on the new machine) to complete. Otherwise, for the rest of the day, I worked on my report.

I worked more on my report today. The beginning is difficult to write for me, as the page progression I am making is VERY slow. However, I believe I am almost done with the set-up portion of the paper and can start analysis soon.

Today was a full paper day. Luckily I'm complete with the introduction and pre-lim stuff so the paper moved by faster. The other bottleneck to writing this paper is to generate the graphs - although I have all the data, it's still time consuming to have the graphs display the way I want them to.

I made some more graphs for my the paper. I also started thinking about the presentation and what I will put in it.