Unfortunately, there was a power surge over the weekend so my compilations got interrupted in the middle. Thus, I was not able to get a lot of data collected over the weekend. The good news is that I got the new computer set up! Oh, wow, it runs SO much faster than the previous one! This one is a multi-tasking computer! After the first of our weekly meetings with Professor Eli this afternoon, I started up running the data for partial mapping. Heh, every experiment now takes around 5-10 minutes instead of the typical I'm-lucky-if-I-can-get-it-under-an-hour times.

Love and I talked more about the partial mapping results. At least for the unconstrained ones, full mapping doesn't work. Professor Eli suggested that loosen up the timing constraints then maybe more components can be mapped. What we found out that when the tool implements the modules unconstrained the logic goes all over the place - the modules are flattened to give the best performance. However, there is very little chance that we can reuse any of the modules, as demonstrated from the experiments. The drawback is that if we use area constraints then not all the components fit on the current board.

Love and I talked more about what's going on with the dataflow graphs. So far, when we take any given test case that worked for partial mapping (for the unconstrained case), we saw that the savings that we get is minimal (~10%). We were discussing a few reasons why there were not enough frames saved. Some of the reasons that I should look into are 1) the randomness of logic and 2) routing difference between the two modules.

I ran some of the full mapping with area constraints after discussing the results from the previous experiments Love and Professor Eli. I ran some full mapping with some area contraints using a bigger board. So far, some mappings work and some don't, depending on where the modules are placed. However, I have found some full mapping placements that work. For those, for any given mapping, they don't have very much variation betweent them. I also tried working on an experiment with wrappers but I can't seem to get them to work so far. I will talk to Love tomorrow about it and see if he can help out.

This morning I finished up some experiments from yesterday and talked to Love about the results and what they mean. He thought that because the spacious design has more area (and thus is looser) than the more compact ones, the routing is less congested and thus we can save more. However, the down side is that it uses up more frames in the first place to reconfigure the board. We also looked the wrappers but we're still running into some slight setbacks. This will be continued later.

This weekend I looked at my data and did some pre-lim work on the graphs I will be using in my final paper.