Week 8: July 26 - 30

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This Week's Goals:

  1. Make slides for my presentation Wednesday.

  2. Complete Task 4 From Last Week - Prepare VPR for experimentation.

    1. Comfirm that all output generated last week is correct.

    2. Add and test outputs pertaining to FPGA and hard macro area.

    3. Finish shell scripts and run trial experiments on a couple small circuits like e64.

    4. Run experiments overnight on the full benchmark suite to see if there are any problems.

    5. Correct errors that occurred during first experimental run - the 6 largest circuits did not complete routing. Additionally, everything but the clma circuit appear to have placed and routed in a reasonable amount of time, but the clma circuit takes over 8 hours to place/route. So, something strange may be going on with this circuit.

      1. VPR has been giving warning messages that its timing-driven placer (the default placer) does not work well with the breadth-first router (which we are using). See if using the bounding-box placer (the one reccomended for use with the breadth-first router) produces better results.

      2. Changing the placement seems to affect whether the routing problem occurs. Thus varying the placer seed (the seed for the random number generator used in the original random layout of logic blocks) might change which circuits route and which don't, possibly giving more insight into what is going on. Try running the trials with a second placer seed to get a better idea of when the routing problem occurs.

      3. Finish solving these problems so the experiments can be completed.

  3. Complete last week's goal 3.2 - Get VPR to handle multiple hard macros and place these hard macros based in information from an input file. Also make sure VPR displays start-up messages for the command line arguments I have added just like it does with the original command line arguments.

    1. Get the code to work with multiple hard macros if the locations of these macros are hard-coded directly into an array.

    2. Create routines similar to the former student's AUTO-FIX feature that will automatically arrange hard macros of a desired size in a symmetric fashion.

    3. Set up VPR to recieve information about how many hard macros will be present, what size they will be, and how big channels around them should be from an input file. Be sure to remove the code that let the size of wide channels be specified as a command line argument, and clean up the print statements pertaining to reading the command line.

    4. Check that multiple hard macros (and the wide channels around them) are not overlapping.

Progress Toward Goals:

  1. Completed Tuesday - I also downloaded ssh software on my home computer so I can run experiments on the unix machine while working on papers and presentations from home. This should be useful in the future.

  2. In Progress at End of Week

    1. Completed Monday - The strange data I was describing last week was due to a TRUE in my code that shoudl have been a FALSE.

    2. Completed Wednesday - In our meeting on Tuesday, my mentor and I decided not to record information about whether FPGA logic blocks are used or empty because this information is difficult to locate in VPR's data structures. This had been the only complicated part of this task, so with this change, the task was not hard to finish.

    3. Completed Wednesday

    4. Completed Thursday - Experiments were run Wednesday night. These experiments were spread over 5 computers (my computer Lucky, and the lab computers Hadrian, Tiberius, Augustus and Claudius) so they would complete faster. If I continue using lab machines for trials, I think I will only use them at night so I will not be occupying the them when others are trying to use them.

    5. In Progress at End of Week:

      1. Completed Friday - Results are much better with this placer. The vast majority of the circuits route, however 3 of them still fail. Oddly, they only fail to route when all of the channels are the same size, routing correctly when wide channels are in place.

      2. Completed Friday - Changing the placer seed does change which circuits route and which ones don't. Something about some of the placements is causing the routing problem.

      3. In Progress at End of Week

  3. In Progress at End of Week:

    1. Completed Thursday

    2. Completed Friday

    3. Completed Friday - It turned out the file would only have had four numbers in it, so I made these values command line arguments instead of the contents of a file.

    4. Not Started at End of Week

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