A Field Programmable Gate Array (FPGA) is is a piece of hardware that can be programmed to change its functionality. Most types of hardware are built to perform a particular function, and cannot do anything else. For example, a device might be made to produce an output that is the sum of its inputs. It will always add its inputs, and it can never change into a device that multiplies or subtracts instead. FPGAs, however, are programmed by computers that set what their functionality will be. At any time, an FPGA can be re-programmed to do something different from what it was doing before.
Structurally, an FPGA is a grid of tiny programmable squares called logic blocks. The spaces between these blocks, called routing channels, are filled with wires. The way these wires connect to each other and to the logic blocks is also programmable, so that a computer can determine how inputs and outputs of logic blocks connect to inputs and outputs of other logic blocks and to those of the FPGA itself.
The computer program needed to program an FPGA is called a placer/router tool. These tools operate in two stages: placement - determining which logic blocks should perform which functions, and routing - determining how wires should connect so that all of the proper inputs and outputs are connected together. A placer/router is given a description, called a circuit design or a netlist, of what the FPGA should do, and from this it determines how the FPGA can be configured to function as desired.
My mentor is interested in FPGAs containing hard macros, devices such as processors, multipliers, and memory blocks, embedded somewhere in the body of the FPGA. She wants to explore whether routing will be easier in FPGAs containing hard macros if the routing channels around the border of the hard macro are larger (containing more wires) than the FPGA's other channels.
I am modifying a placer/router tool (written in C) called Versatile Placer/Router (VPR) for use in this study. We want VPR to take a circuit design that does not involve any hard macros, and choose a group of logic blocks from that design to represent a hard macro for the purposes of our experiments. These logic blocks will be placed together in a small square region of the FPGA, and I will ensure that no wires that do not connect to these logic blocks enter that region. In this way, it will be similar to a hard macro, which is a solid device that FPGA wires could not pass through. I am also changing VPR to allow routing channels around our "hard macro" to be widened.
When the modifications are complete, I will use the new version of VPR to place and route a test suite of circuit designs (called the MCNC Benchmark Suite), allowing me to investigate how easy routing is, with and without wider channels around the "hard macro" VPR creates.