Where am I, and how did I get here?

     The Distributed Mentoring Project (DMP) is a subset of the Committee on the Status of Women in Computing Research. Each summer, female undergraduates are matched up with a faculty mentor at colleges and universities all across the United States and Canada for the purpose of conducting research for ten weeks in the field of computer science.

     I am very fortunate to have been selected as a DMP participant this summer. I have been assigned to work with Dr. Kelly Shaw in the Department of Mathematics & Computer Science at the University of Richmond in the beautiful state of Virginia. The campus is quite stunning, there's even a lake! (Please see "Instant Replays"). Each summer, a few dozen UR students are bestowed the title of Research Associate and given grants. So, much to my initial surprise, I am the only visiting student here this summer; quite the novelty!

     Typically, most assignments are in the physical and life sciences (biology, chemistry, biochemistry) and this summer is no different. Excluding myself, there are seven other research associates in computer science, whose work is linked with the biochem department. The remaining student is Yuri Dogandjiev, (he's from Bulgaria!) who is also working with Dr. Shaw on a different, but related project.


What's the game plan?

     My research this summer will examine the use of commercial workloads on single-chip, multiprocessor architectures. Commercial workloads are large databases supporting online transaction processing (OLTP) applications used by such companies and web servers as banks and bookstores.

     Unfortunately, over 35% of execution time for OLTPs is spent stalling while threads retrieve data that has been transferred to another cache. While a small amount of work has previously been done on increasing thread efficiency (reducing latency), none has investigated why these cache-to-cache transfers are happening.

     It is my aim to discover what is happening at the software level to cause the transference of cached data in shared memory systems. I plan to do this by first looking at how data is used across threads, which instructions are issuing these threads, and what memory addresses they access. Next, instructions associated with data sharing will be mapped back to the application to determine what parts of the program are triggering the transfers.

Ultimately, Dr. Shaw and I hope to not simply reduce these "useless misses", but eliminate them by moving computation to data, rather than data to the computation.