Monday already? Wow, weekend goes by fast when you code, code, code. I continued doing MAC syntheses today. I should be done by the end of tomorrow, as I only have 4 more sets to go. I made such a dumb mistake today, I wrote my verilog code wrong for one of the 16-bit sets and that caused me about an extra hour's worth of work. Remind me to check my code twice before I click synthesize. Code that compiles doesn't mean it's correct! I meet with Professor Eli on Wednesday at 11:30. I hope I'll have something for her by then.

This morning, I finished up the 16-bit sets and and started on the 32-bit sets of MACs. I am on track tofinish up all the MACs by this afternoon. Unfortunately, the 64-bit sets take up a lot of resources, so my computer is pretty much a single-task computer for the rest of the time. I finished the downloads page, just need to put in the right files. Somehow, life has suddenly gotten really hectic. I really need that computer at work to run faster. I don't see how I'm going to get all the syntheses and the other work done otherwise.

I ran some more syntheses this morning on the adder-multiplier this morning before I met with Professor Eli and Love at 11:30. We talked about mostly about Love's project, what direction he's going to go move, and what my next part should be. We discussed more about frames and constraints. Professor Eli suggested that I make a graph of the bit-widths and how they relate to the clock frequency, frames, and CLBs. She said that optimization of modules doesn't only rely on shape and the number of CLBs. She also mentioned that I should do a constrained and a unconstrained version to see what the software would do if left by itself. After lunch, Love and I further discussed how to calculate the bits and the overhead it needs. He showed me how to use bitgen to do the calculations so from now on, I will incorporate this into my notes. Professor Eli mentioned that she was going to buy a new desktop for me to use (yay! =D). Until then, I set up Xilinx on Richa's computer and will be using two computers to run my syntheses.

Today, Love and I talked about the frames needed per merged module and how to figure that out using Xilinx. When he demoed on his computer, he did it with one multiplier and it looked pretty easy. Unfortunately, when I got back to my computer, I couldn't figure out how to do it for two modules. Love mentioned that if I can't grab the merged module as one module, I go back and talk to him again. I did that, Love got it working and I started looking at the frames as well the area. This changes my procedure slightly, as now I must place the modules within the proper CLBs on the board instead of just anywhere not close to the processor.

Love and I talked more today about the timing constraints. He said (along with Professor Eli) that it's actually very important to have the constraint as tight as possible. A large over-estimate like I had earlier (10 ns regardless of module) doesn't give the best timing. So, for any given module, I needed to pay attention and predict a good time. If I go too low, then the tool keeps grinding and eventually gives a time that it was able to obtain, but it may not be the best time. Love mentioned that he'd like a report sometime next week of all my data. Remind to never tell him again how long I think the data collection will take - for the last few things, I always seem to shoot myself in the foot. In this case, the data collection's taking a very long time.

Love mentioned that the new update packages came out for the software and that I should download them. Well, I did, and I realized that the CORE Generator's package update actually is a very big change. Two majors ones were that the dividers were different (giving me different data) and that there no non-DSP Slice multipliers available. That...made things much more difficult. I still had the older models so I'm just going to use those until I talk to Love later.

I ran a lot of syntheses this weekend and I hopefully will be done with all the data soon. I'm doing a lot tighter timing constraints now with the data, so I'm fairly sure of all the timings. The problem is that when I give it too tight of one, Xilinx will always finish but the amount of time it takes can take forever. I ran one (yes, only one) synthesis on a 16-bit module and it ended up taking 1 hour, 23 min, and 36 seconds REAL time. UGH.

On a side note, as per DMP specifications, I updated/am in the process of updating my website so it can be more of a standalone thing.

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