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Project Description

A Field Programmable Gate Array (FPGA) is a prefabricated integrated circuit chip with Combinational Logic Blocks (CLBs) ordered into a grid configuration. The FPGA chip has no manufactured function, instead it is ‘programmable’; the user can create a circuit design and change the configuration of the FPGA chip to that of the design. Opposed to traditional integrated circuit chips, FPGAs can be programmed with numerous designs many number of times. This is what makes FPGAs useful, they allow for practical testing of new circuit chips without manufacturing the chip.

This project will examine performance and reconfiguration time based on the physical layout of applications on chip. This is interesting because to get the most efficient usage out of the FPGA chip, the user has to understand the difference between the two variables. For example, the user who has finished design and partial testing of an application might want to run the application on chip a million times. If the application runs at nominal speed because its layout is optimized for minimum reconfiguration time, then multiplied by a million times the slow run time makes for inefficient testing. Conversely, if the user is still testing and debugging, the user might want to reconfigure the chip a hundred times before a particular bug is sorted. If the application layout is optimized for performance, then the chip might run fast, but take longer to reconfigure. Multiply this by a hundred times and it becomes inefficient for the user to reconfigure often. So the key here is the physical layout of the application on chip. Depending on the layout, the chip might run fast but reconfigure slowly, or reconfigure fast but run slowly, or ideally, reconfigure and run fast.

Reconfiguration Overhead in Dynamic Task Based Implementation on FPGAs (pdfs)

Research Paper 

Final Presentation Slides

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